1. Field of the Invention
The present invention is related to circuit simulation by over-approximation techniques that reduce simulation burden over that of exhaustive analysis, and more specifically to simulation programs, methods and system that use symbolic states in the results of the simulation to enhance the simulation, perform netlist reduction and other model simplification.
2. Description of Related Art
Logic simulators typically verify designs of processor integrated circuits (ICs), as well as other large-scale logic, by observing certain behaviors during the simulation process and reducing the netlist that describes the logic in various ways using the information gathered during the simulation process.
One part of the simulation performed on such devices is reachability analysis, which in present systems is typically an approximate reachability analysis that, through certain assumptions, reduces the amount of time to approximate very closely the state-space that can be reached by the logic in a device, or a portion of a device being simulated. By using values of initial state including both binary states as well as an unknown state, behavior of the logic can be observed and any logic output that appears to resolve to one of the two known states, or to a pattern oscillating between the two known states, can be simplified. Through this process, the simulation can be trimmed dynamically while in process, leading to an approximate, but generally valid description of the state flow of the logic that is obtained in a far shorter time than would be possible with exhaustive simulation.
However, due to the very large and increasing size of logic designs, even existing techniques are time-consuming and memory intensive. Therefore, it would be desirable to provide a simulation program, method and system that have improved performance and/or reduced memory requirements.